American Audio UCD-200 - REV 8-10 Specifications Page 31
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For the cap interface, this feature can be disabled by setting bit D0 of control register 20H/page 2. In the case
of the cap-less interface, VGND short circuit protection must also be disabled, which can be achieved by setting
bit D4 of control register 21H/page 2.
The TSC2111 implements a pop reduction scheme to reduce audible artifacts during powerup and powerdown
of headphone drivers. The scheme can be controlled by programming bits D5 and D4 of control register
25H/page 2. By default, the driver pop reduction scheme is enabled and can be disabled by programming bit
D5 of control register 25H/page 2 to 1. When this scheme is enabled and the virtual ground connection is not
used (VGND amplifier is powered down), the audio output driver slowly charges up any external ac-coupling
capacitors to reduce audible artifacts. Bit D4 of control register 25H/page 2 provides control of the charging time
for the ac-coupling capacitor as either 0.8 sec or 4 sec. When the virtual ground amplifier is powered up and
used, the external ac-coupling capacitor is eliminated, and the powerup time becomes 1 ms. This scheme takes
effect whenever any of the headphone drivers are powered up.
D Speaker Driver
The TSC2111 has an integrated speaker driver (OUT8P−OUT8N) capable of driving an 8 Ω differential load.
The speaker driver, powered directly from the battery supply (3.5 V to 4.2 V) on the BVDD pin can deliver 400
mW at 3.9 V supply. It allows connecting one or both DAC channel to speaker driver. The TSC2111 also has a
short circuit protection feature for the speaker driver which can be enabled by setting bit D5 of control register
21H/page 2.
D Receiver Driver
The TSC2111 includes a receiver driver (SPK1−OUT32N), which can drive a 32 Ω differential load. It is
capable of delivering 82 mW into a 32 Ω load. The TSC2111 does not allow both the receiver driver and
headphone drivers to be turned on at the same time. Also, when the receiver driver is being used, the
headphone driver load must be disconnected.
D Simultaneous DAC Playback to Headphone and Speaker Outputs
The TSC2111 allows simultaneous DAC playback by using the BUZZ_IN PGA to route the SPL1 and SPK2
signals to the OUT8P and OUT8N drivers (bits D7 and D6, Register 25h, page 2). By utilizing the BUZZ_IN
PGA fully independent volume control of the headphone and of the speaker driver outputs are achieved.
Headset Interface
The TSC2111 supports all standard headset interfaces. It is capable of interfacing with 3-wire stereo headset,
3-wire cellular headset and 4-wire stereo-cellular headsets. It supports both capacitor-coupled (cap) and
capacitor-less (capless) interface for headset through software programming.
D Capless Interface
Figure 22 shows the connection diagram to the TSC2111 for capless interface. VGND acts as a ground of
headset jack. Voltage at VGND is 1.5 V and MICBIAS_HED voltage is programmed to 3.3 V. With this, the
voltage across microphone is configured to be 1.8 V. In order to minimize the effect of routing resistance on
VGND inside the device and on the printed circuit board (PCB), SPKFC should be shorted to VGND at the
jack. This reduces crosstalk from speaker to microphone because of common ground as VGND.
- Serial Interface 1
- PACKAGE/ORDERING INFORMATION 2
- PIN ASSIGNMENTS 2
- Terminal Functions 3
- ABSOLUTE MAXIMUM RATINGS 4
- ELECTRICAL CHARACTERISTICS 5
- FUNCTIONAL BLOCK DIAGRAM 10
- SPI TIMING DIAGRAM 11
- TYPICAL TIMING REQUIREMENTS 11
- Figure 3. I 13
- TYPICAL CHARACTERISTICS 15
- OVERVIEW 19
- OPERATION—AUDIO CODEC 19
- D Word Select Signals 20
- D Bitclock (BCLK) Signal 20
- D 256-S Transfer Mode 20
- D Continuous Transfer Mode 20
- D Right Justified Mode 20
- D Left Justified Mode 21
- D DSP Mode 21
- D When PLL is disabled 22
- D When PLL is enabled 23
- D Set and enable PLL 24
- Automatic Gain Control (AGC) 25
- Table 3. AGC Settings 26
- D Headphone Drivers 29
- D Speaker Driver 31
- D Receiver Driver 31
- D Capless Interface 31
- D Cap Interface 32
- D Auto Detection 33
- D Headset Detection 34
- D Button Detection 34
- OPERATION—TOUCH SCREEN 35
- PLL enabled 39
- PLL disabled 39
- Temperature 44
- R + 50 KW 45
- VREF * Vsar 45
- DIGITAL INTERFACE 47
- PAGE 1 CONTROL REGISTER MAP 51
- REGISTER 01H: Status Register 52
- REGISTER 02H: Buffer Control 54
- REGISTER 04H: Reset Control 55
- REGISTER 0EH: Reserved 58
- PAGE 2 CONTROL REGISTER MAP 59
- REGISTER 04H: Audio Control 2 62
- REGISTER 06H: Audio Control 3 64
- REGISTER IDH: Audio Control 4 68
- REGISTER 20H: Audio Control 5 71
- REGISTER 21H: Audio Control 6 72
- REGISTER 22H: Audio Control 7 73
- REGISTER 23H: GPIO Control 74
- REGISTER 26H: Mic AGC Control 77
- Port Scan Operation 86
- PACKAGE OPTION ADDENDUM 93
- PACKAGE MATERIALS INFORMATION 95
- IMPORTANT NOTICE 100
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