American Audio UCD-200 - REV 8-10 Specifications download pdf (Page 23)

100

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SLAS495A− JUNE 2006 − REVISED OCTOBER 2007

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D When PLL is enabled

Fsref +

MCLK K

2048 P

P = 1, 2, 3 … 8

K = J.D

J = 1, 2, 3 ….63

D = 0, 1, 2 … 9999

P, J and D are register programmable. where J is integer part of K before the decimal point, and D

is four-digit fractional part of K after the decimal point, including lagging zeros.

Examples: If K = 8.5, then J = 8, D = 5000

If K = 7.12, then J = 7, D = 1200

If K = 7.012, then J = 7, D = 120

The PLL is programmed through Registers 1BH and 1CH of Page 2.

D When PLL is enabled and D = 0, the following conditions must be satisfied

2MHzv

MCLK

v 20 MHz

80 MHz v

MCLK K

v 110 MHz

4Ă v J vĂ55

D When PLL is enabled D ≠ 0, the following conditions must be satisfied

10 MHz v

MCLK

v 20 MHz

80 MHz v

MCLK K

v 110 MHz

4Ă v J vĂ11

Example 1:

For MCLK = 12 MHz and Fsref = 44.1 kHz

P = 1, K = 7.5264

J = 7, D = 5264

Example 2:

For MCLK = 12 MHz and Fsref = 48 kHz

P = 1, K = 8.192

J = 8, D = 1920

Table 1. Fsref = 44.1 kHz

MCLK (MHz) P J D ACHIEVED FSREF % ERROR

2.8224 1 32 0 44100.00 0.0000

5.6448 1 16 0 44100.00 0.0000

12.0 1 7 5264 44100.00 0.0000

13.0 1 6 9474 44099.71 −0.0007

16.0 1 5 6448 44100.00 0.0000

19.2 1 4 7040 44100.00 0.0000

19.68 1 4 5893 44100.30 0.0007

48 4 7 5264 44100.00 0.0000

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American Audio UCD-200 - REV 8-10 Specifications Page 23

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